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general description the max11040k/max11060 are 24-/16-bit, 4-channel, simultaneous-sampling, sigma-delta analog-to-digital converters (adcs). the devices allow simultaneous sampling of as many as 32 channels using a built-in cascade feature to synchronize as many as eight devices. the serial interface of the devices allows read- ing data from all the cascaded devices using a single command. four modulators simultaneously convert each fully differential analog input with a programmable data output rate ranging from 0.25ksps to 64ksps. the devices achieve 106db snr at 16ksps and 117db snr at 1ksps (max11040k). the devices operate from a single +3v supply. the differential analog input range is ?.2v when using the internal reference; an external reference is optional. each input is overvoltage protect- ed up to ?v without damage. the devices use an internal crystal oscillator or an external source for clock. the devices are compatible with spi, qspi, microwire, and dsp-compatible 4-wire serial inter- faces. an on-board interface logic allows one serial inter- face (with a single chip select) to control up to eight cascaded devices or 32 simultaneous sampling analog input channels. the devices are ideally suited for power-management systems. each channel includes an adjustable sam- pling phase enabling internal compensation for phase shift due to external dividers, transformers, or filters at the inputs. the output data rate is adjustable with a 0.065% resolution (at 16ksps or below) to track the varying frequency of a periodic input. a sync input allows periodic alignment of the conversion timing of multiple devices with a remote timing source. the devices are available in a 38-pin tssop package speci- fied over the -40? to +105? industrial temperature range. applications power-protection relay equipment multiphase power systems industrial data-acquisition systems medical instrumentation features four fully differential simultaneously sampled channels cascadable for up to 32 channels of simultaneous sampling 106db (max11040k) snr at 16ksps 117db (max11040k) snr at 1ksps 0.25% error over a 1000:1 dynamic range, processed over 16.7ms (max11040k) ?.2v full-scale input range ?v overvoltage protected inputs internal crystal oscillator 2.5v, 50ppm/? internal reference or external reference programmable output data rate 0.25ksps to 64ksps range 0.065% resolution programmable sampling phase 0 to 333 s delay in 1.33 s steps spi-/qspi-/microwire-/dsp-compatible 4-wire serial interface cascadable interface allows control of up to eight devices with a single cs signal 3.0v to 3.6v analog supply voltage 2.7v to v avdd digital supply voltage 38-pin tssop package max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ________________________________________________________________ maxim integrated products 1 19-5741; rev 2; 11/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package max11040k guu+ -40? to +105? 38 tssop max11060 guu+ -40? to +105? 38 tssop microwire is a trademark of national semiconductor corp. spi/qspi are trademarks of motorola, inc. max11040k max11060 24-/16-bit adc digital filter 2.5v reference crystal oscillator refio ain3+ ain3- ref3 24-/16-bit adc digital filter ain2+ ain2- ref2 24-/16-bit adc digital filter ain1+ ain1- ref1 24-/16-bit adc digital filter ain0+ ain0- ref0 registers and digital control serial interface dout din sclk cs cascout cascin drdyout drdyin sync fault ovrflw clkout xout dgnd agnd xin functional diagram
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v av dd = +3.0v to +3.6v, v dv dd = +2.7v to v av dd , f xin clock = 24.576mhz, f out = 16ksps, v refio = +2.5v (external), c refio = c ref0 = c ref1 = c ref2 = c ref3 = 1? to agnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to agnd ........................................................-0.3v to +4v dvdd to dgnd ......................................-0.3v to (v avdd + 0.3v) agnd to dgnd.....................................................-0.3v to +0.3v din, sclk, cs , xin, sync , drdyin , cascin to dgnd..............................-0.3v to (v dvdd + 0.3v) dout, drdyout , cascout, clkout, xout to dgnd..................................-0.3v to (v dvdd + 0.3v) fault , ovrflw to dgnd ...................................-0.3v to +4.0v ain_+ to ain_- ......................................................-6.0v to +6.0v ain_ _ to agnd (v avdd 3v, v dvdd 2.7v, faultdis = 0, shdn = 0, f xin clock 20mhz)......................-6.0v to +6.0v ain_ _ to agnd (v avdd < 3v or v dvdd < 2.7v or faultdis = 1 or shdn = 1 or f xin clock < 20mhz) ..............-3.5v to +3.5v refio, ref_ to agnd............................-0.3v to (v avdd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) tssop (derated 13.7mw/? above +70?)..............1096mw operating temperature range .........................-40? to +105? storage temperature range .............................-60? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units dc accuracy (note 2) max11040k 24 resolution max11060 16 bits differential nonlinearity dnl 24-b i t no mi ssing cod e ( m ax11040k) ; 16-b i t no mi ssing cod e ( m ax 11060) 0.1 lsb t a = +25c and + 105c (max11040k) 0.001 0.004 t a = -40? (max11040k) 0.006 integral nonlinearity (note 3) inl max11060 0.001 %fs offset error -1 +1 mv gain error (note 4) -1 +1 %fs offset-error drift (note 5) 0.5 ppm/? gain-error drift (note 5) 1 ppm/? change in gain error vs. f out f out = 0.25ksps to 64ksps < 0.025 % fs channel-to-channel gain matching 0.03 % fs dynamic specifications (62.5hz sine-wave input, 2.17v p-p ) (note 6) (max11040k) 103 106 signal-to-noise ratio snr (note 6) (max11060) 94.5 db t a = + 25c and + 105c ( m ax 11040k) -94 t a = -40? (max11040k) -90 total harmonic distortion thd max11060 -106 db t a = + 25c and + 105c ( m ax 11040k) 93 98 t a = -40? (max11040k) 89 signal-to-noise plus distortion sinad max11060 94 db t a = + 25c and + 105c ( m ax 11040k) 94 100 t a = -40? (max11040k) 89 spurious-free dynamic range sfdr max11060 100 db 0.1%fs input (max11040k) 0.25 relative accuracy (note 7) 6.0%fs input (max11040k) 0.005 %
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units bandwidth -3db 3.4 khz latency (note 8) 405 s passband flatness from dc to 1.4khz < 0.1 db amplitude-dependent phase error fs vs. 0.1% fs < 0.01 0.12 degrees channel-to-channel phase matching 0.0001 degrees phase-error drift 0.001 degrees channel-to-channel isolation -130 db common-mode rejection cmrr 109 db analog inputs (ain_+, ain_-) differential fs input range v in v ain_+ - v ain_- -2.2 +2.2 v single-ended positive input range v ain_+ referenced to agnd -2.2 +2.2 v single-ended negative input range v ain_- referenced to agnd -2.2 +2.2 v positive fault threshold v pft v ain_+ or v ain_- (note 9) 2.25 2.65 v negative fault threshold v nft v ain_+ or v ain_- (note 9) -2.65 -2.25 v fault pin response time 2.5 s v nft v in v pft 130 input impedance z in v in < v nft or v in > v pft > 0.5 k dc leakage current i in v ain_ + = v ain_ - 0.01 1 a input sampling rate f s f s = f xinclock /8 3.072 msps input sampling capacitance 4.0 pf internal reference refio output voltage v ref t a = t max 2.4 2.5 2.6 v refio output resistance 1k refio temp drift 50 ppm/c refio long-term stability 200 ppm/ 1000hr refio output noise 3v rms refio power-supply rejection psrr 75 db external reference refio input voltage v ref 2.3 2.7 v refio sink current 200 a refio source current 200 a refio input capacitance 10 pf crystal oscillator (xin, xout) tested resonant frequency (note 10) 24.576 mhz maximum crystal esr 30 oscillator startup time < 2 ms oscillator stability v dvdd = 3.3v, excluding crystal 10 ppm/c m axi m um o sci l l ator load 10 pf electrical characteristics (continued) (v av dd = +3.0v to +3.6v, v dv dd = +2.7v to v av dd , f xin clock = 24.576mhz, f out = 16ksps, v refio = +2.5v (external), c refio = c ref0 = c ref1 = c ref2 = c ref3 = 1f to agnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1)
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v av dd = +3.0v to +3.6v, v dv dd = +2.7v to v av dd , f xin clock = 24.576mhz, f out = 16ksps, v refio = +2.5v (external), c refio = c ref0 = c ref1 = c ref2 = c ref3 = 1f to agnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units digital inputs (sclk, cs , din, sync , cascin, drdyin , xin) input low voltage v il 0.3 x v dvdd v input high voltage v ih 0.7 x v dvdd v input hysteresis v hys v dvdd = 3.0v 100 mv input leakage current i l 0.01 1a input capacitance c in 15 pf cmos digital outputs (dout, cascout, drdyout , clkout) output low voltage v ol i sink = 5ma 0.15 x v dvdd v output high voltage v oh i source = 1ma 0.85 x v dvdd v three-state leakage current i lt 1 a three-state capacitance c out 15 pf open-drain digital outputs ( ovrflw , fault ) output low voltage v ol i sink = 5ma 0.15 x v dvdd v output high voltage v oh internal pullup only 0.85 x v dvdd v internal pullup resistance 30 k ? power requirements analog supply voltage av dd 3.0 3.6 v digital supply voltage dv dd 2.7 v avdd v normal operation 25 35 ma analog supply current (note 11) i avdd shutdown and f xinclock = 0hz 0.1 5 a normal operation 11 15 ma digital supply current (note 11) i dvdd shutdown and f xinclock = 0hz 0.3 a ac positive-supply rejection v avdd = 3.3v + 100mv p-p at 1khz 70 db dc positive-supply rejection v avdd = v dvdd = 3.0v to 3.6v 75 db esd protection all pins esd human body model 2.5 kv timing characteristics (figures 7?0) sclk clock period t scp 50 ns sclk pulse width (high and low) t pw 20 ns din or cs to sclk fall setup t su 10 ns sclk fall to din hold t hd 0ns sclk rise to cs rise t csh1 0ns
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs _______________________________________________________________________________________ 5 note 1: devices are production tested at +105c. specifications to -40c are guaranteed by design. note 2: tested at v av dd = v dv dd = +3.0v. note 3: integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors ar e removed. note 4: offset nulled. note 5: offset and gain drift defined as change in offset and gain error vs. full scale. note 6: noise measured with ain_+ = ain_- = agnd. note 7: relative accuracy is defined as the difference between the actual rms amplitude and the ideal rms amplitude of a 62.5hz sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal rms amplitude. the rela- tive accuracy specification refers to the maximum error expected over 1 million measurements. calculated from snr. not production tested. note 8: latency is a function of the sampling rate and xin clock. note 9: voltage levels below the positive fault threshold and above the negative fault threshold, relative to agnd on each individ- ual ain_+ and ain_- input, do not trigger the analog input protection circuitry. note 10: test performed using rxd mp35. note 11: all digital inputs at dgnd or dvdd. note 12: sync is captured by the subsequent xin clock if this specification is violated. note 13: delay from dvdd exceeds 2.0v until digital interface is operational. electrical characteristics (continued) (v av dd = +3.0v to +3.6v, v dv dd = +2.7v to v av dd , f xin clock = 24.576mhz, f out = 16ksps, v refio = +2.5v (external), c refio = c ref0 = c ref1 = c ref2 = c ref3 = 1f to agnd, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) parameter symbol conditions min typ max units c load = 30pf 1.5 10 16 sclk rise to dout valid t dot c load = 100pf < 16 ns cs fall to dout enable t doe c load = 30pf 0.3 20 ns cs rise to dout disable t dod c load = 30pf 0.7 16 ns cs pulse width t csw 16 ns cascin-to-sclk rise setup t sc 16 ns sclk rise to cascout valid t cot c load = 100pf 20 ns sync pulse width t syn 2 xin clock cycles xin clock pulse width t xpw 16 ns drdyin to drdyout t drdy c load = 30pf 20 ns xin clock to drdyout delay t xdrdy drdyin = dgnd 40 ns xin clock period t xp 40 ns xin clock to sync setup t ss (note 12) 16 ns sync to xin clock hold t hs (note 12) 5 ns xin-to-clkout delay t xcd 40 ns power-on reset delay (note 13) < 1 ms
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 6 _______________________________________________________________________________________ typical operating characteristics (max11040k) (v av dd = v dv dd = 3.3v, f xin clock = 24.576mhz, f out = 16ksps, v refio = 2.5v (external), c refio = c ref0 = c ref1 = c ref2 = c ref3 = 1f, t a = +25c, unless otherwise noted.) inl vs. differential input voltage max11040k/11060 toc01 differential input voltage (v) inl (% fs) 1.5 0.5 -0.5 -1.5 -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0.004 0.005 -0.005 -2.5 2.5 histogram of rms amplitude at 0.1% fs max11040k/11060 toc02 rms amplitude (% fs) instances 50 100 150 200 250 300 350 400 450 500 0 0.09970 0.09976 0.09982 0.09988 0.09994 0.10000 0.10006 0.10012 0.10018 0.10024 0.10030 maximum expected error of calculated rms amplitude vs. input amplitude max11040k/11060 toc03 input amplitude (% fs) maximum expected error (%) 10 1 0.1 0.01 0.1 1 0.001 0.01 100 1 million 62.5hz cycles signal-to-noise ratio vs. output data rate max11040k/11060 toc04 output data rate (ksps) snr (db) 10 1 90 100 110 120 130 80 0.1 100 fft vs. frequency at full scale max11040k/11060 toc05 frequency (hz) amplitude (db fs) 7000 6000 5000 4000 3000 2000 1000 -120 -100 -80 -60 -40 -20 0 -140 0 8000 60hz sine-wave input fft vs. frequency at 0.1% full scale max11040k/11060 toc06 frequency (hz) amplitude (db fs) 7000 6000 5000 4000 3000 2000 1000 -160 -140 -120 -100 -80 -60 -40 -180 0 8000 60hz sine-wave input rms amplitude vs. input frequency max11040k/11060 toc07 input frequency (hz) rms amplitude (db) 1000 100 -0.4 -0.3 -0.2 -0.1 0 0.1 -0.5 10 10,000 rms amplitude gain error vs. output data rate max11040k/11060 toc08 output data rate (hz) rms amplitude gain error (%) 10,000 1000 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -0.05 100 100,000 rms amplitude vs. source resistance max11040k/11060 toc09 source resistance ( ) rms amplitude (db) 10,000 1000 100 -8 -7 -6 -5 -4 -3 -2 -1 0 1 -9 10 100,000
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs _______________________________________________________________________________________ 7 total harmonic distortion vs. input frequency max11040k/11060 toc10 input frequency (hz) thd (db) 1500 1000 500 -120 -110 -100 -90 -80 -130 0 2000 offset error vs. supply voltage max11040k/11060 toc11 supply voltage (v) offset error (% fsr) 3.5 3.4 3.3 3.2 3.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 3.0 3.6 avdd = dvdd offset error vs. temperature max11040k/11060 toc12 temperature ( c) offset error (% fsr) 76 47 18 -11 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 -40 105 avdd = dvdd gain error vs. supply voltage max11040k/11060 toc13 supply voltage (v) gain error (% fsr) 3.4 3.3 3.2 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 3.0 3.5 3.6 avdd = dvdd gain error vs. temperature max11040k/11060 toc14 temperature ( c) gain error (% fsr) 60 35 10 -15 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -40 85 v avdd = v dvdd = 3.3v gain error drift max11040k/11060 toc15 time (hr) gain error (%) 900 800 700 600 500 400 300 200 100 -0.08 -0.06 -0.04 -0.02 0 -0.10 0 1000 typical operating characteristics (max11040k continued) (v av dd = v dv dd = 3.3v, f xin clock = 24.576mhz, f out = 16ksps, v refio = 2.5v (external), c refio = c ref0 = c ref1 = c ref2 = c ref3 = 1f, t a = +25c, unless otherwise noted.)
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 8 _______________________________________________________________________________________ typical operating characteristics (max11040k continued) (v av dd = v dv dd = 3.3v, f xin clock = 24.576mhz, f out = 16ksps, v refio = 2.5v (external), c refio = c ref0 = c ref1 = c ref2 = c ref3 = 1f, t a = +25c, unless otherwise noted.) supply current vs. supply voltage max11040k/11060 toc16 supply voltage (v) supply current (ma) 3.5 3.4 3.3 3.2 3.1 5 10 15 20 25 30 0 3.0 3.6 avdd = dvdd i avdd i dvdd supply current vs. temperature max11040k/11060 toc17 temperature ( c) supply current (ma) 76 47 18 -11 5 10 15 20 25 30 0 -40 105 v avdd = v dvdd = 3.3v i avdd i dvdd shutdown supply current vs. supply voltage max11040k/11060 toc18 supply voltage (v) supply current (na) 3.5 3.4 3.3 3.2 3.1 100 200 300 400 500 0 3.0 3.6 avdd = dvdd i avdd i dvdd shutdown supply current vs. temperature max11040k/11060 toc19 temperature ( c) supply current (na) 76 47 18 -11 200 400 600 800 1000 0 -40 105 v avdd = v dvdd = 3.6v i avdd i dvdd crystal oscillator startup time max11040k/11060 toc20 40 s/div clkout 500mv/div
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs _______________________________________________________________________________________ 9 pin description pin name function 1 ain0- negative analog input channel 0 2 ain0+ positive analog input channel 0 3 ref0 adc0 buffered reference voltage. bypass ref0 with a 1f capacitor to agnd. 4, 8, 10, 29, 31, 35 agnd analog ground 5 ain1- negative analog input channel 1 6 ain1+ positive analog input channel 1 7 ref1 adc1 buffered reference voltage. bypass ref1 with a 1f capacitor to agnd. 9 refio reference voltage output/input. reference voltage for analog-to-digital conversion. in internal reference mode, the reference buffer provides a +2.5v nominal output. in external reference mode, overdrive refio with an external reference between 2.3v to 2.7v. bypass refio with a 1f capacitor to agnd. 38 37 36 35 34 33 32 1 2 3 4 5 6 7 ain2- ain2+ ref2 agnd agnd ref0 ain0+ ain0- top view max11040k max11060 ain3- ain3+ ref3 ref1 ain1+ 31 8 agnd agnd 30 9 avdd refio 29 10 agnd agnd 28 11 dgnd dgnd 27 12 dvdd dvdd 26 13 xin cascin 25 14 xout cascout ain1- 24 15 sync cs 23 16 drdyin sclk 22 17 drdyout din 21 18 clkout dout 20 19 ovrflw fault tssop + pin configuration
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 10 ______________________________________________________________________________________ pin description (continued) pin name function 11, 28 dgnd digital ground 12, 27 dvdd positive digital supply voltage. bypass each dvdd to dgnd with a 1f capacitor in parallel with a 0.01f capacitor as close as possible to the device. 13 cascin cascade input. a logic-low on cascin while cs is a logic-low during the last cycle of a byte signals the device to perform the requested data transfer during subsequent bytes using din and dout. once the requested transfer is completed, the part three-states dout and ignores din until a new command is issued. cascin is clocked in at the rising edge of sclk. connect cascin to dgnd when not daisy chaining multiple devices. see the multiple device connection section for connection recommendations. 14 cascout cascade output. cascout is driven low during the last cycle of the last byte of a data transfer to signal the next device in the daisy-chain to begin transferring data on the next byte. cascout changes after the rising edge of sclk. leave cascout unconnected when not daisy chaining multiple devices. see the multiple device connection section. 15 cs active-low chip-select input. a falling edge on cs while cascin is a logic-low enables din and dout for data transfer. a logic-high on cs prevents data from being clocked in on din and places dout in a high-impedance state. 16 sclk serial-clock input. clocks in data at din on the falling edge of sclk and clocks out data at dout on the rising edge of sclk. sclk must idle high (cpol = 1). 17 din serial data input. data at din is clocked in on the falling edge of sclk. 18 dout serial data output. the drive for dout is enabled by a falling edge on cs while cascin is low or by a falling edge on cascin while cs is low. dout is disabled/three-stated when cs is high or after the appropriate number of data bytes have been transferred in response to the requested command. data is clocked out at dout on the rising edge of sclk. 19 fault acti ve- low o ver vol tag e faul t ind i cator outp ut. f au lt g oes l ow w hen any anal og i np ut g oes outsi d e the faul t thr eshol d r ang e ( b etw een v p ft and v n ft ) . the f au lt outp ut i s op en d r ai n w i th a 30k i nter nal p ul l up r esi stor , al l ow i ng w i r e- n or functi onal i ty. s ee the anal og inp ut over vol tag e and faul t p r otecti on secti on. 20 ovrflw active-low channel data overflow output. ovrflw goes low when a conversion result goes outside the voltage range bounded by the positive and negative full scale on one or more of the analog input channels or when fault goes low. the ovrflw output is open drain with a 30k internal pullup resistor, allowing wire-nor functionality. see the analog input overvoltage and fault protection section. 21 clkout buffered clock output. when the xtalen bit in the configuration register is 1 and a crystal is installed between xin and xout, clkout provides a buffered version of the internal oscillators clock. setting the xtalen bit to 0 places clkout in a high-impedance state.
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 11 pin description (continued) pin name function 22 drdyout active-low data ready output. when drdyin = 0, drdyout outputs a logic-low to indicate the availability of a new conversion result. drdyout transitions high at the next cs falling edge or when drdyin = 1. see the multiple device connection section. 23 drdyin active-low data ready input. a logic-high at drdyin causes drdyout to output a logic-high. when drdyin = 0, drdyout outputs a logic-low when a new conversion result is available. see the multiple device connection section. connect drdyin to dgnd when not daisy chaining multiple devices. 24 sync sampling synchronization input. the falling edge of sync aligns sampling and output data so that multiple devices sample simultaneously. synchronize multiple devices running from independent crystals by connecting drdyout of the last device in the chain to the sync inputs of all devices in the chain. connect sync to dgnd for single device operation. see the multiple device connection section. 25 xout crystal oscillator output. connect a 24.576mhz external crystal or resonator between xin and xout when using the internal oscillator. leave xout unconnected when driving with an external frequency. see the crystal oscillator section. 26 xin crystal oscillator/clock input. connect a 24.576mhz external crystal or resonator between xin and xout when using the internal oscillator or drive xin with an external clock and leave xout unconnected. see the crystal oscillator section. 30 avdd positive analog supply voltage. bypass to agnd with a 1f capacitor in parallel with a 0.01f capacitor as close as possible to the device. 32 ref3 adc3 buffered reference voltage. bypass with a 1f capacitor to agnd. 33 ain3+ positive analog input channel 3 34 ain3- negative analog input channel 3 36 ref2 adc2 buffered reference voltage. bypass with a 1f capacitor to agnd. 37 ain2+ positive analog input channel 2 38 ain2- negative analog input channel 2
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 12 ______________________________________________________________________________________ detailed description the max11040k/max11060 are 24-/16-bit, simultane- ous-sampling, 4-channel, sigma-delta adcs including support for synchronized sampling and daisy chaining of the serial interface across multiple (up to eight) devices. the serial interface of the set of synchronized devices behaves as one device. each channel includes a differential analog input, a sigma-delta modulator, a digital decimation filter, an independent programmable sampling delay, and a buffered reference signal from the internal or an external reference. the device con- tains an internal crystal oscillator. the output data rate, the effective sample rate of the adc, is software pro- grammable. the devices operate from a single 3.0v to 3.6v analog supply and a 2.7v to v avdd digital supply. the 4-wire serial interface is spi/qspi/microwire and dsp com- patible. adc modulator each channel of the devices performs analog-to- digital conversion on its input using a dedicated switched-capacitor sigma-delta modulator. the modula- tor converts the input signal into low-resolution digital data for which the average value represents the digitized sig- nal information at 3.072msps for a 24.576mhz xin clock. this data stream is then presented to the digital filter for processing to remove the high-frequency noise that cre- ates a high-resolution 24-/16-bit output data stream. the input sampling network of the analog input consists of a pair of 4pf capacitors (c sample ), the bottom plates of which are connected to ain_+ and ain_- dur- ing the track phase and then shorted together during the hold phase (see figure 1). the internal switches have a total series resistance of 400 . given a 24.576mhz xin clock, the switching frequency is 3.072mhz. the sampling phase lasts for 120ns. max11040k max11060 c sample+ hold to adc r on r on c sample- track track ain_+ ain_- avdd/2 figure 1. simplified track/hold stage max11040k max11060 ain0+ ain0- 1 f ain0- ain0+ 24.576mhz ref0 ain1+ ain1- 1 f ain1- ain1+ ref1 ain2+ ain2- 1 f ain2- ain2+ ref2 ain3+ ain3- 1 f ain3- ain3+ ref3 1 f refio 0.01 f 1 f 3.3v avdd 0.01 f 1 f 3.3v dvdd 20pf 20pf xin xout clkout cascout cascin dout drdyout din sclk cs sync drdyin fault ovrflw microcontroller or dsp agnd dgnd typical operating circuit
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 13 digital filter the devices contain an on-chip digital lowpass filter that processes the data stream from each modulator and generates the high-resolution output data. the low- pass filter frequency response is determined by the programmable output data rate. at the nominal 16ksps output data rate, the -3db bandwidth of the filter is 3.4khz. the passband flatness is better than 0.1db from 0 to 1.74khz. the notches are located at 5.75khz and 7.195khz. these frequencies scale linearly with the output data rate. see figure 2 and table 1 for the fre- quency response at different data rates. since the transfer function of a digital filter is repeatable and predictable, it is possible to correct for frequency- dependent attenuation in downstream software. see the compensating for the rolloff of the digital filter in a typical fft analysis section. the transfer function is defined by the following equation: where: gain is the filter gain. f ain is the analog input frequency. f sample is the programmed output data rate, nominally 16khz. f xinclock is the clock frequency at xin, nominally 24.576mhz. fir_gain (f ain ) is the normalized gain of the fir filter with the following filter coefficients, as a function of the analog input frequency f ain . these coefficients are applied at the output data rate: + 0.022 - 0.074 - 0.036 + 0.312 + 0.552 + 0.312 - 0.036 - 0.074 + 0.022 gain f f f f f ain sample ain sample () sin = ? ? ? ? ? ? x xinclock ain xinclock f f ? ? ? ? ? ? ? ? ? ? ? ? ? ? sin ? ? ? ? ? ? ? () 3 _() fir gain f ain table 1. bandwidth vs. output data rate output data rate (ksps) -3db bandwidth (khz) -0.1db bandwidth (khz) 0.5 0.11 0.05 1 0.21 0.11 2 0.42 0.22 4 0.85 0.43 8 1.69 0.87 10 2.11 1.09 12 2.54 1.31 16 3.38 1.74 32 6.78 3.48 64 13.5 6.96 max11040k fig02 f ain /f sample gain (db) 0.24 0.20 0.16 0.12 0.08 0.04 -5 -4 -3 -2 -1 0 1 -6 0 0.28 figure 2. digital filter response
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 14 ______________________________________________________________________________________ modulator clock the modulator clock is created by dividing the frequen- cy at the xin input by a factor of 8. the xin input is dri- ven either directly by an external clock or by the on-chip crystal oscillator. crystal oscillator the on-chip oscillator requires an external crystal (or resonator) with a 24.576mhz operating frequency con- nected between xin and xout, as shown in figure 3. as in any crystal-based oscillator circuit, the oscillator frequency is sensitive to the capacitive load (c l ). c l is the capacitance that the crystal needs from the oscilla- tor circuit and not the capacitance of the crystal. the input capacitance across xin and xout is 1.5pf. choose a crystal with a 24.576mhz oscillation frequen- cy and an esr less than 30 , such as the mp35 from rxd technologies. see figure 3 for the block diagram of the crystal oscillator. set xtalen = 1 in the configu- ration register to enable the crystal oscillator. the clkout output provides a buffered version of the clock that is capable of driving eight devices, allowing synchronized operation from a single crystal. see the multiple device synchronization section in the applications information section. external clock to use an external clock, set xtalen = 0 in the configuration register and connect an external clock source (20mhzC25mhz) to xin. clkout becomes high impedance. analog input overvoltage and fault protection the full-scale differential input range of the devices is 0.88v ref . the converter accurately represents any input for which the positive and negative analog inputs are separated by a magnitude of less than 0.88v ref . the device includes special circuitry that protects it against voltages on the analog inputs up to + 6v. setting faultdis = 1 disables the protection circuitry. there are two mechanisms of overvoltage detection and protection: full-scale overflow and overvoltage fault. full-scale overflow occurs if the magnitude of the applied input voltage on any one or more channels is greater than 0.88v ref . in this case, the digital output is clipped to positive or negative full scale and the ovrflw flag goes low. overvoltage fault occurs if the magni- tude of an applied input voltage on any one or more channels goes outside the fault-detection thresholds. the reaction to an overvoltage fault is dependent on whether the fault-protection circuitry is enabled. if enabled, the input-protection circuits engage and the fault flag goes low. a full-scale overflow or an over- voltage fault condition on any one channel does not affect the output data for the other channels. the input protection circuits allow up to 6v relative to agnd on each input, and up to 6v differentially between ain+ and ain-, without damaging the devices only if the following conditions are satisfied: power is applied, the devices are not in shutdown mode, a clock frequency of at least 20mhz is available at xin, and faultdis = 0. the analog inputs allow up to 3.5v rel- ative to agnd when either devices are placed in shut- down mode, the clock stops, or faultdis = 1. during an overvoltage fault condition, the impedance between ain_+ and ain_- reduces to as low as 0.5k . the output structure and cascading features of fault and ovrflw are discussed in the multiple device digital interface section. analog input overflow detection and recovery ( ovrflw ) the ovrflw flag is set based on the adc conversion result. when the applied voltage on one or more analog inputs goes outside the positive or negative full scale (0.88v ref ), ovrflw asserts after a delay defined by the latency of the converter, coincident with the drdyout of the full-scale clamped conversion result (see figure 4). the specifics of the latency are discussed earlier in the data sheet in the latency section. max11040k max11060 24.576mhz 20pf 20pf xin xout 24.576mhz oscillator figure 3. crystal oscillator input
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 15 when the analog input voltage changes between the adc full scale and the fault threshold faster than the latency of the converter, ovrflw goes low with the fault output. ovrflw remains invalid until a valid clock frequency is available at xin. overvoltage-fault detection and recovery ( fault ) with overvoltage-fault protection enabled (faultdis = 0), fault immediately transitions from a high to low when any of the analog inputs go outside the voltage range bounded by the fault-detection thresholds v pft and v nft . once the analog inputs return back within the fault thresholds, the fault interrupt output goes high after a delay called the fault-recovery time. the fault-recovery time is: 20 x t dout < fault-recovery time < 25 x t dout where t dout is the data output period determined by f xinclock and the selected output data rate. in the event the analog input voltage changes between the adc full scale and the fault threshold faster than the latency of the converter, the adc conversion result prematurely jumps to the full-scale value when a fault is detected (see detection discontinuity in figure 4). during a fault condition and the subsequent fault- recovery time, the adc conversion result remains at full scale. this creates a discontinuity in the digital conver- sion result only if the fault recovery time is greater than the latency plus the time that the input changes between the fault threshold and the adc full scale (see recovery discontinuity in figure 4). neither of these steps occur if the fault-protection circuitry is disabled (faultdis = 1), or if the input is slow relative to the above descriptions (see figure 5). for data rates faster than 32ksps (fsampc = 111), the converter output may contain invalid data for up to 188s after fault returns high. to prevent this behav- ior, disable the overvoltage-fault protection by setting the faultdis bit in the configuration register to 1 when using fsampc = 111, and limit the analog input swing to 3.5v. |ain+ - ain-| latency latency latency detection discontinuity recovery discontinuity full scale (|0.88v ref |) fault-detection threshold (v pft or |v nft |) recovery time latency fault ovrflw digital output data at dout figure 4. high-frequency analog input overvoltage detection and recovery
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 16 ______________________________________________________________________________________ |ain+ - ain-| full scale (|0.88v ref |) fault-detection threshold (v pft or |v nft |) fault ovrflw recovery time latency latency latency digital output data at dout latency figure 5. low-frequency analog input overvoltage detection and recovery reference the devices operate with either a +2.5v internal bandgap reference or an external reference source between +2.3v and +2.7v applied at refio. bypass refio and each ref_ to agnd with a 1f capacitor. the reference voltage sets the positive and negative full-scale voltage according to the following formula: fs = 0.88 v refio the reference voltage at refio (external or internal) is individually buffered to generate the reference voltages at ref0 to ref3 (see figure 6.) these independent buffers minimize the potential for crosstalk between each of the internal adcs. serial interface the devices interface is fully compatible with spi/dsp standard serial interfaces (compatible with spi modes cpol = 1, cpha = 0). the serial interface provides access to four on-chip registers: sampling instant control register (32 bits), data rate control register (16 bits), configuration register (8 bits), and data register (96 bits). all serial-interface commands begin with a command byte, which addresses a specific register, followed by data bytes with a data length that depends on the specific register addressed and the number of devices cascaded (see figures 7, 8, and the registers section). the serial interface consists of eight signals: cs , sclk, din, dout, cascin, cascout, drdyin , and drdyout . cascin, cascout, drdyin , and drdyout are used for daisy chaining multiple devices together. see the multiple device connection section for details on how to connect cascin, cascout, +2.5v reference refio ref3 ref2 ref1 ref0 figure 6. refio input
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 17 drdyin , and drdyout . for single-device applications, connect cascin and drdyin to dgnd and drive cs low to transfer data in and out of the devices. with drdyin low, a falling edge at the data-ready signal out- put ( drdyout ) indicates that new conversion results are available for reading in the 96-bit data register. a falling edge on sclk clocks in data at din. data at dout changes on the rising edge of sclk and is valid on the falling edge of sclk. din and dout are trans- ferred msb first. drive cs high to disable the interface and place dout in a high-impedance state. an interface operation with the devices takes effect on the last rising edge of sclk. if cs goes high before the complete transfer, the write is ignored. every data transfer is initiated by the command byte. the com- mand byte consists of an r/ w bit and 7 address bits (see table 2.) figures 7 and 8 show the timing for read and write operations, respectively. t csw sclk cs din dout drdyin high-z high-z b7 b6 b5 b4 b3 b2 b1 b0 t su t scp t dcd t csh1 t su t doe t drdy data ready t hd command address t dot t pw t pw r/w a6 a5 a3 a2 a1 a0 a4 data length (number of bytes) depends on the register being read (see table 2) drdyout figure 7. general read-operation timing diagram dout high-z high-z t csw t su t hd t su t pw t scp t pw t csh1 cs din sclk a6 a5 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 r/w b0 data length (number of bytes) depends on the register being written (see table 2) a4 figure 8. general write-operation timing diagram
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 18 ______________________________________________________________________________________ registers the devices include four registers accessible by 7 command bytes. the command bytes provide read and write access to the data rate control register, the sampling instant control register, and the configuration register, and read access to the data register. see table 2. figure 9 shows the cascin and casout timing diagram. figure 10 is the xin clock, clkout, sync , and drdyout timing diagram. table 2. command bytes r/ w address [a6:a0] data length* function 0 1000000 32 x n** bits write sampling instant control register 1 1000000 32 x n bits read sampling instant control register 0 1010000 16 bits write data-rate control register 1 1010000 16 bits read data-rate control register 0 1100000 8 x n bits write configuration register 1 1100000 8 x n bits read configuration register 1 1110000 96 x n bits read data register *all data lengths are proportional to the number of cascaded devices except for reads and writes to the data rate control register. when accessing the data rate control register, the data length is fixed at 16 bits. these 16 bits are automatically written to all cascaded devices. **n is the total number of cascaded devices. sclk cascout (device n) cascin (device n+1) t sc t cot figure 9. cascin and cascout timing diagram xin clock sync clkout drdyout t xp t xpw t xcd t ss t hs t xdrdy t syn figure 10. xin clock, clkout, sync , and drdyout timing diagram
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 19 sampling instant control register by default, the devices sample all 4 input channels simultaneously. to delay the sampling instant on one or more channels, program the appropriate byte in the sampling instant control register. the delay of the actual sampling instant of each individual channel from the default sampling instant (phi_[7:0] = 0x00) is adjustable between 32 to 819,121 xin clock cycles, which is 1.3s to 333s with f xinclock at 24.576mhz (see table 3.) configuration register the configuration register contains 5 bits that control the functionality of the devices. the default state is 0x00. the data length of the configuration register is 8 bits per cascaded device (see table 4). table 3. sampling instant control register bit name description [31:24] phi0[7:0] channel 0 sample instant adjust. phi0 delays sampling instant on channel 0 by 32 xin clock cycles per lsb, up to 8192 cycles total (1.3s resolution; 333s range at xin of 24.576mhz). [23:16] phi1[7:0] channel 1 sample instant adjust. phi1 delays sampling instant on channel 1 by 32 xin clock cycles per lsb, up to 8192 cycles total (1.3s resolution; 333s range at xin of 24.576mhz). [15:8] phi2[7:0] channel 2 sample instant adjust. phi2 delays sampling instant on channel 2 by 32 xin clock cycles per lsb, up to 8192 cycles total (1.3s resolution; 333s range at xin of 24.576mhz). [7:0] phi3[7:0] channel 3 sample instant adjust. phi3 delays sampling instant on channel 3 by 32 xin clock cycles per lsb, up to 8192 cycles total (1.3s resolution; 333s range at xin of 24.576mhz). table 4. configuration register bit name description 7 shdn shutdown bit. set shdn high to place the device in shutdown mode. in shutdown mode, the internal oscillator, fault circuitry, and internal bandgap reference are turned off. set shdn low for normal operation. 6 rst reset bit. set rst high to reset all registers to the default states except for the rst bit, and realign sampling clocks and output data. 5 en24bit enable 24-bit resolution bit for the max11040k. set en24bit high to enable the 24-bit data output. set en24bit low to enable 19-bit data output with device address and channel address tags. tables 5 and 6 specify the data register for both states of this bit. set to 0 for max11060. 4 xtalen internal oscillator enable bit. when using the on-chip crystal oscillator as the clock source, set xtalen high to enable the crystal oscillator and provide a buffered version of the crystal clock at the clkout output. when using an external clock source, set xtalen low to disable the internal crystal oscillator and three- state the clkout output. connect the external clock source to the xin input. 3 faultdis overvoltage fault-protection disable bit. set faultdis high to disable the overvoltage fault-protection circuits. for faultdis = 0, the absolute maximum input range is 6v. analog inputs beyond the fault- detection threshold range trip the fault-protection circuits. the output remains clipped for a fault-recovery time (typically < 1.57ms) after the inputs return within the fault-detection threshold range. for faultdis = 1, the absolute maximum input range is only 3.5v, but there is no fault-recovery delay. see the overvoltage fault detection and recovery (fault) section. 2 pdbuf pdbuf = 1 disables the internal reference buffer. use this mode when an external reference is used; otherwise, pdbuf should be set to 0 to enable the internal reference buffer. [1:0] reserved must set to 0.
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 20 ______________________________________________________________________________________ data register the data register contains the results of the adc con- version. the result is reported in twos complement for- mat. the register contains one or two pieces of information, depending on the state of en24bit in the configuration register. when en24bit is set to zero, the data register contains the adc data truncated to 19 bits, followed by the device and channel addresses (see table 5). when en24bit is set to one, the data contained in the data register represents the 24-bit conversion (see table 6). the data length of the data register is 96 bits for each cascaded device. figure 11 shows the sequence of the conversion result output of all channels for two cascaded devices. table 7 is the data register for the max11060. if the results are not read back prior to completion of the next conversion, the data is overwritten. table 5. data register (en24bit = 0) (max11040k) bit name description [95:77] ch0data[18:0] channel 0 19-bit conversion result (twos complement) [76:74] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [73:72] 00 channel 0 address tag = 00 [71:53] ch1data[18:0] channel 1 19-bit conversion result (twos complement) [52:50] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [49:48] 01 channel 1 address tag = 01 [47:29] ch2data[18:0] channel 2 19-bit conversion result (twos complement) [28:26] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [25:24] 10 channel 2 address tag = 10 [23:5] ch3data[18:0] channel 3 19-bit conversion result (twos complement) [4:2] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [1:0] 11 channel 3 address tag = 11 table 6. data register (en24bit = 1) (max11040k) bit name description [95:72] ch0data[23:0] channel 0 24-bit conversion result (twos complement) [71:48] ch1data[23:0] channel 1 24-bit conversion result (twos complement) [47:24] ch2data[23:0] channel 2 24-bit conversion result (twos complement) [23:0] ch3data[23:0] channel 3 24-bit conversion result (twos complement) table 7. data register (max11060) bit name description [95:80] ch0data[15:0] channel 0 16-bit conversion result (twos complement) [79:77] 000 [76:74] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [73:72] 00 channel 0 address tag = 00 [71:56] ch1data[15:0] channel 1 16-bit conversion result (twos complement) [55:53] 000 [52:50] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [49:48] 01 channel 1 address tag = 01 [47:32] ch2data[15:0] channel 2 16-bit conversion result (twos complement)
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 21 data rate control register the data rate control register controls the output data period, which corresponds to the output data rate of the adc. the data period is controlled by both a coarse (fsampc[2:0]) and a fine (fsampf[10:0]) adjustment (see table 8). the final data rate is derived by dividing the xin clock frequency by a divider value. the divider value is a function of fsampc[2:0] and fsampf[10:0]: data rate = f xinclock /divider divider = coarse cycle factor x 384 + fine cycle factor x fsampf[10:0] note: fractional results for the divider are rounded down to the nearest integer. coarse cycle factor and fine cycle factor come from table 8. the effect of fsampf[10:0] in the formula has limitations as noted in the table. examples of output data rate vs. fsampc[2:0] and fsampf[10:0] are shown in table 9. table 10 shows typical device performance for various data rate settings. cs din sclk dout cascout0 (cascin0 = 0) drdyout0 (drdyin0 = 0) drdyout1 cascout1 device 0 data ready device 0 and device 1 data ready 24 cycles channel 0 device 0 channel 1 device 0 channel 2 device 0 channel 3 device 0 channel 0 device 1 channel 1 device 1 channel 2 device 1 channel 3 device 1 24 cycles 24 cycles 24 cycles 24 cycles 24 cycles 24 cycles 24 cycles device 1 takes over spi bus figure 11. 192-bit data read operation diagram for two cascaded devices table 7. data register (max11060) (continued) bit name description [31:29] 000 [28:26] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [25:24] 10 channel 2 address tag = 10 [23:8] ch3data[15:0] channel 3 16-bit conversion result (twos complement) [7:5] 000 [4:2] ic[2:0] device address tag. ic[2:0] starts with 000 for the device nearest the master. [1:0] 11 channel 3 address tag = 11
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 22 ______________________________________________________________________________________ drdyout cs data read change data rate 1 2 15 16 17 data at the old data rate data at the new data rate figure 12. timing diagram for a data-rate change the data length of the data-rate control register is 16 bits total for writes and reads (see table 2). changes to the data-rate control register take effect after 16 con- version periods (figure 12), i.e., the adc continues to operate at the old data rate for another 16 periods. also, the last sample at the old data rate (sample 16 in figure 12) may contain some noise component and should be discarded. changes in data rate should be limited to 5% for correct operation. the data rate register should not be updated more than once every 32 data rate peri- ods. note: write to the data rate register in the time window of 10ns after the rising edge of drdyout and 100ns before the falling edge of drdyout . the digital filter determines the latency. latency is defined as the time between the effective point in time that a sample is taken and when the resulting digital data is available for reading ( drdyout goes low). the laten- cy of the converter is specified by the following equation: latency = (6 x t dout ) + (phi x 1.3s) + 30s where t dout is the data output period (inverse of the programmed sample rate) determined by xinclock and the selected output data rate, and phi is the pro- grammed sampling instant delay for the channel in ques- tion (0 phi 255). the latency is approximately 405s at 16ksps. because the two filters operate at different output data rates, a skew builds up between them over the 16 sam- ples that both are in operation. for example, at 30ksps, the minimum data rate step size is 0.125%; so over 16 samples, the difference becomes 2%. this causes the period from sample 16 to sample 17 to be different by this amount.
max11040k/max11060 table 8. data-rate control register bits name description output data rate coarse adjust bits. fsampc[2:0] sets the coarse cycle factor. fsampc coarse cycle factor sample rate in ksps (f xin clock = 24.576mhz) 000 4 16 001 128 0.5 010 64 1 011 32 2 100 16 4 101 8 8 110 2 32 [15:13] fsampc[2:0] 111 1 64 [12:11] reserved set to 0. output data rate fine adjusts bits. fsampf[10:0] increases the output data period by a number of xin clock cycles. this number is the value of the register times the fine cycle factor. values of fsampf greater than 1535 have no additional effect. fsampc xin fine cycle factor 000 1 cycle 001 32 cycles 010 16 cycles 011 8 cycles 100 4 cycles 101 2 cycles 110 1 cycle [10:0] fsampf[10:0] 111 1 cycle table 9. examples of output data rate as a function of fsampc[2:0] and fsampf[10:0] fsampc[2:0] fsampf[10:0] output data rate (sps) output data period (24.576mhz clock cycles) fsampf output data period resolution (24.576mhz clock cycles) 11xxxxxxxxx 250.1 98272 10111111111 250.1 98272 00000000001 499.7 49184 001 00000000000 500.0 49152 32 11xxxxxxxxx 500.2 49136 10111111111 500.2 49136 00000000001 999.3 24592 010 00000000000 1000.0 24576 16 11xxxxxxxxx 1000.3 24568 10111111111 1000.3 24568 00000000001 1998.7 12296 011 00000000000 2000.0 12288 8 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 23
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 24 ______________________________________________________________________________________ table 9. examples of output data rate as a function of fsampc[2:0] and fsampf[10:0] (continued) fsampc[2:0] fsampf[10:0] output data rate (sps) output data period (24.576mhz clock cycles) fsampf output data period resolution (24.576mhz clock cycles) 11xxxxxxxxx 2000.7 12284 10111111111 2000.7 12284 00000000001 3997.4 6148 100 00000000000 4000.0 6144 4 11xxxxxxxxx 4001.3 6142 10111111111 4001.3 6142 00000000001 7994.8 3074 101 00000000000 8000.0 3072 2 11xxxxxxxxx 8002.6 3071 10111111111 8002.6 3071 00000000001 15990 1537 000 00000000000 16000 1536 1 11xxxxxxxxx 16010 1535 1011111111x 16010 1535 0000000001x 31958 769 110 0000000000x 32000 768 1 11xxxxxxxxx 32042 767 101111111xx 32042 767 000000001xx 63834 385 111 000000000xx 64000 384 1 table 10. typical performance vs. output data rate output data rate (ksps) -3db bandwidth (khz) -0.1db bandwidth (khz) latency (?) fault recovery time (?) snr of 24-bit data (db) relative accuracy of 256 data points (%) relative accuracy of single cycle at 60hz (%) 0.5 0.11 0.05 12030 16375 117 0.04 0.23 1 0.21 0.11 6030 8375 115 0.05 0.20 2 0.42 0.22 3030 4375 113 0.06 0.17 4 0.85 0.43 1530 2375 111 0.08 0.16 8 1.69 0.87 780 1375 108 0.11 0.16 10 2.11 1.09 630 1175 107 0.13 0.16 12 2.54 1.31 530 1042 106 0.14 0.16 16 3.38 1.74 405 875 105 0.16 0.16 32 6.78 3.48 218 625 97 0.40 0.28 64 13.5 6.96 124 500 81 2.51 1.26
max11040k/max11060 max11040k max11060 sync cs sclk din cascin drdyin drdyout fault ovrflw dout xin device n+1 device 0 device n max11040k max11060 sync cs sclk din cascin drdyin cascout fault ovrflw dout xin xout clkout max11040k max11060 sync cs sclk din cascin drdyin cascout fault ovrflw dout xin dsp or microcontroller cascade up to 8 devices figure 13. daisy chaining multiple devices 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 25 multiple device connection daisy chain up to eight devices for applications that require up to 32 simultaneously sampled inputs over a single spi-/dsp-compatible serial interface with a single chip-select signal, and single interface commands that apply to all devices in the chain. the eight devices effec- tively operate as one device. there are two aspects to cascading multiple devices: the digital interface and the mechanism for keeping multiple devices sampling simultaneously. there are many configurations for connecting multiple devices; one is described in the next section, others are described in the synchronizing multiple devices section within the applications information section. multiple device digital interface figure 13 shows the most common way to daisy chain the digital interface of multiple devices. spi bus arbitration is performed using cascin and cascout. a falling edge at the cascin input of device n, which is driven by the cascout of device n-1, allows device n to take over the spi bus until all expect- ed data is written or read; at this point, device n pulls its cascout output low. similarly, cascout of device n drives cascin of device n+1. figures 12 and 14 show read operations, including cascin and cascout tim- ings, for two cascaded devices and eight cascaded devices, respectively. the operation described above applies to all register operations except for writes to the data-rate control register. a fixed 16-bit word is written to the data-rate control registers of all devices in the chain, independent of the number of cascaded devices (see figure 15). reading from the data-rate control register returns 16 bits per cascaded device. connecting the open-drain ovrflw output of all devices together creates one signal that summarizes the overflow information of all devices. this is also true of the fault output. connecting together these out- puts from multiple devices has the effect of a wire nor. any device that has an active condition on these outputs is allowed to pull the line low.
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 26 ______________________________________________________________________________________ din sclk dout t csw cascout0 (cascin0 = 0) cascout1 cascout2 cascout3 cascout4 cascout5 cascout6 cascout7 cs device 0 device 1 device 2 device 3 device 4 device 5 device 6 device 7 figure 14. configuration register read operation timing diagram for eight cascaded devices there are two ways to use a single line to indicate that all devices have their data ready, depending on whether they are clocked synchronously. if all devices have the same xin clock and have been synchronized using sync or reset commands, the drdyout of any device in the chain is used to represent all of them. alternatively, if the devices use a different xin clock, connect drdyin of device 0 to ground, and connect drdyin of device n to the drdyout of device n-1 for all devices. drdyout does not go low until drdin is low and the conversion of the device is complete. in this configuration, drdyout of the last device goes low only when all devices in the chain have their data ready.
max11040k/max11060 din b15 b14 b13 x x b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sclk dout high-z high-z cascout0 (cascin0 = 0) cascout1 cascout2 cascout3 cascout4 cascout6 cascout5 cascout7 x = reserved cs figure 15. data rate controller register write operation timing diagram for eight cascaded devices 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 27
s s y y n n c c for simultaneous sampling with multiple devices the sync input permits multiple devices to sample simultaneously. the mismatch between the power-up reset of multiple devices causes the devices to begin conversion at different times. after a falling edge on the sync input, the device completes the current conver- sion and then synchronizes subsequent conversions (see figure 16). upon a sync falling edge, the devices measure the time between the sync falling edge to the preceding drdy- out falling edge, wait until the next drdyout falling edge, then pause the adc for the measured amount of time. figure 16 shows an example where the converter is regularly sampling the input and producing a drdy- out with a period t s . the effect of a sync falling edge as shown in figure 16 is described in sequence below: 1) a sync falling edge is issued two xin clock cycles after the drdyout event 2. 2) the converter remembers the two xin clock cycles, and completes the current sample, issuing drdyout event 3 a period of t s after drdyout event 2. 3) then, the converter pauses for the remembered time period, two xin clock cycles for this example. 4) correspondingly, drdyout event 4 is issued two xin cycles later than it would have without the sync falling edge. 5) the process continues as normal with drdyout event 5 appearing t s after drdyout event 4. max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 28 ______________________________________________________________________________________ xin note: the latency is not to scale. drdyout sync ain_ measure pause delay 2 cycles t s t s t s t s t s t s t s t s t s t s 1 1 2 2 3 3 4 4 5 5 6 figure 16. effect of a sync falling edge
referring back to the analog input, since the entire sam- pling section of the converter also paused for two clock cycles, the sampling point for sample 5 is also paused by two clock cycles, possibly creating a small distur- bance at the sync falling edge. this disturbance is fil- tered with the digital filter, which makes it less distinct. if the sync falling edge occurred during the same xin clock period as the drdyout signal, the disturbance does not affect the periodic timing since the sync falling edge would demand a pause of zero xin clock cycles. hence, connecting the drdyout of one con- verter to the sync inputs of many converters, as illus- trated in figure 13, aligns the sampling of the converters on the first sync falling edge, but does not disturb a regular sampling process for future samples. see the multiple device synchronization section for dif- ferent ways to use the sync input. transfer function figures 17 shows the bipolar i/o transfer function. code transitions occur halfway between successive- integer lsb values. output coding is binary, with 1 lsb = (0.88 x v refio ) x 2/524,288 in 19-bit mode, (0.88 x v refio ) x 2/16,777,216 in 24-bit mode, and (0.88 x v refio ) x 2/65536 for the max11060. power-on reset the serial interface, logic, digital filter, and modulator circuits reset to zero at power-up. the power-on reset circuit releases this reset no more than 1ms after v dv dd rises above 2v. max11040k/max11060 output code differential input voltage (lsb) fs fs - 3/2 lsb 0 -fs full-scale transition *n = 19 for 19-bit transfer function, n = 24 for 24-bit transfer function fs = +0.88 x v refio zs = 0 -fs = -0.88 x v refio 1 lsb = 2(0.88 x v refio ) 2 n* 100...001 100...000 111...110 000...010 011...111 011..110 000...011 000...001 000...000 111...111 n = 16 for max11060 figure 17. adc transfer function 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 29
applications information multiple device synchronization synchronizing multiple devices using a shared xin clock source to synchronize multiple devices sharing a single xin clock source, transition the sync input that is shared by all devices high to low. when an external sync source is not available, connect drdyout of one device to the sync input of all devices in the chain. the devices ignore any sync transitions applied dur- ing the power-on reset. synchronizing multiple devices using independent xin clock sources if it is undesirable to connect the xin clock sources together, due to emi or other reasons; use drdyin , drdyout , and sync to align the conversion timing as shown in figure 18. this minimizes the effects of drift between the clock sources by resynchronizing after each conversion when drdyout transitions low. in this configuration, the maximum correction caused by a sync edge is one xin clock cycle. the resulting sampling rate is determined by the sampling frequency of the device with the slowest clock source, plus the delay through the drdyin to drdyout chain between this slowest device and the end of the chain. synchronizing multiple devices to an independent clock source to periodically synchronize multiple devices to an inde- pendent timing source, connect the timing source to the sync inputs of the devices. if minimal jitter is important in the application, program the devices to a frequency slightly slower than the external frequency, such that sync falling edges only occur a short time after the drdyout signals. max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 30 ______________________________________________________________________________________ max11040k max11060 sync cs sclk din cascin drdyin drdyout fault ovrflw dout xin device n+1 device 0 device n max11040k max11060 sync cs sclk din cascin drdyin cascout fault ovrflw dout xin xout clkout max11040k max11060 sync cs sclk din cascin drdyin cascout drdyout fault ovrflw dout xin xout xout drdyout dsp or microcontroller cascade up to 8 devices figure 18. one crystal per device and all sync inputs driven by drdyout of the last device in the chain
max11040k/max11060 discontinuity due to sync event drdyout sync measure t dryout_to_sync ain_ reconstructed digital output pause for t dryout_to_sync note: the latency is not to scale. t dryout_to_sync 1 1 2 3 4 2 3 4 5 6 1 2 3 4 5 6 t s t s t s t s t s t s t s t s t s figure 19. example of discontinuity in reconstructed digital output due to sync falling edge with a large drdyout -to- sync delay 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 31 signal distortion at sync falling edges each sync falling edge causes a disruption in the digi- tal filter timing proportional to the delay from the previ- ous falling edge of drdyout to the falling edge of sync . any analysis of the output data that assumes a uniform sampling period sees an error proportional to that delay, with a maximum value determined by the maximum derivative of the analog input. figure 19 shows the effect of this discontinuity at output sample 5. assuming a 60hz 2.2v sine wave, the maximum pos- sible error on any given sample caused by a sync falling edge is: v error_max = 2.2v x 2 x 60hz x t drdyout _to_ sync = 0.83v/ns x t drdyout _to_ sync the delay from drdyout to sync is quantized to within one cycle of the 24.576mhz clock. sync pulses that are asynchronous to drdyout may cause large errors. to eliminate this error, use a single clock source for all devices and avoid disrupting the output data tim- ing with sync pulses while making high-precision measurements. alternately, minimize the delay from drdyout to sync to minimize the error. example: assume f ain_ = 60hz, f s = 16ksps, and eight total devices in the chain. device 1 has the longest t drdyout _to_ sync delay, therefore the worst-case sync error. if device 1 has the fastest xin clock in the chain, and device 2 has the slowest xin clock in the chain, and they differ by 0.1%, device 1 completes its conversion as much as 0.1% earlier than device 2. hence, the delay of device 2 is: 0.1% x (1/16khz ) = 62.5ns the signal then propagates down the chain at a time delay of nominally 20ns for each device. the total delay back to the sync falling edge after going through six additional delays is: t delay = 62.5ns + 6 x 20ns = 182.5ns maximum % error = 2 x f in x t drdyout _to_ sync x 100% = 2 x x 60hz x 182.5ns x 100% = 0.007% the above error is relative to the signal level, not to the full scale of the data converter.
source impedance and input sampling network the source impedance that drives the analog inputs affects the sampling period. low-impedance sources minimize the source impedance to ensure the input capacitor fully charges during the sampling phase. the required source resistance is defined by the equation below: where k = 1.5 and r int = 2600 . for example, the required source resistance to achieve 0.1% accuracy is: high-impedance sources if the source impedance is greater than r source_max , as defined in the low-impedance sources section, place a 0.1f bypass capacitor between ain_+ and ain_- to provide transient charge. the average switched-capacitor load with a proper bypass capacitor and xin clock frequency = 24.576mhz is equivalent to a 130k resistor connect- ed between ain_+ and ain_-. this resistance is inde- pendent of the value of the 0.1f bypass capacitor. if another xin clock frequency is chosen, this resistance is directly proportional to the xin clock period. although the addition of a bypass capacitor helps charge the devices 0 input capacitor, some gain error due to resistive drop across the source resistance still remains. calculate this gain error using the following equation: analog filtering the analog filtering requirements in front of the devices are considerably reduced compared to a conventional converter with no on-chip filtering. the internal digital filter has significant rejection of signals higher than the nyquist frequency of the output data rate that would alias back into the sampled signal. the internal digital filter does not provide rejection close to the harmonics of the 3.072mhz modulator fre- quency. for example, assuming an output data rate of 16ksps if the xin clock is set to 24.576mhz, then the band between 3.0686mhz and 3.0750mhz is not explicitly filtered. since this unfiltered band is very small compared to its actual frequency, very little broadband noise enters through this mechanism. if focused narrowband noise in this band is present, a simple analog filter can create significant attenuation at this frequency because the ratio of passband-to-stop- band frequency is large. in addition, because the devices common-mode rejec- tion extends out to several 100khz, the common-mode noise susceptibility in this frequency range is substan- tially reduced. providing additional filtering in some applications ensures that differential noise signals outside the fre- quency band of interest do not saturate the analog modulator. the modulator saturates if the input voltage exceeds its full scale (2.2v). the digital filter does not prevent a large signal in the filter stopband from saturating the modulator. if signals outside the band of interest cause violation of this full scale while accurate conversion of passband signals is desired, then additional analog fil- tering is required to prevent saturation. compensating for the rolloff of the digital filter in typical fft analysis to calculate fir_gain(f ain_ ): 1) decide the number of evenly spaced frequencies between dc and the nyquist frequency of the output data rate at which correction factors are desired, which is usually the same as the fft result. 2) create an array with a length that is 2x the number of the desired frequencies. (again, the result is likely to correlate with the time domain array that is loaded into an fft algorithm.) 3) fill this array with the filter coefficients provided in the digital filter section. fill the rest of the array with zeros. 4) take an fft of this array. the result represents the response of the devices built-in fir filter. gain r rr r rk source source load source source = + = + 130 r ns xpfx ns xpfx ns xpfx source max _ . ln .% . ln . . < ? ? ? ? ? ? = () == ? ? ? 120 15 4 1 01 2600 120 1 5 4 1000 2600 120 15 4 691 2600 294 ? r t kxc xin error r ns xpfxin error source max samp samp int _ . < ? ? ? ? ? ? = ? ? ? ? ? ? ? ? 1 120 15 4 1 2600 max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 32 ______________________________________________________________________________________
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs ______________________________________________________________________________________ 33 to compensate the result of an fft for the devices out- put data: 1) calculate the inverse (1/x) of the equation provided in the digital filter section for each frequency in the fft. 2) multiply the fft of the devices output data by the result of the above step. power supplies avdd and dvdd provide power to the devices. the avdd powers up the analog section, while the dvdd powers up the digital section. the power supply for avdd and dvdd ranges from +3.0v to +3.6v and 2.7v to v avdd , respectively. bypass avdd to agnd with a 1f electrolytic capacitor in parallel with a 0.1f ceramic capacitor and bypass dvdd to dgnd with a 1f elec- trolytic capacitor in parallel with a 0.1f ceramic capaci- tor. for improved performance, place the bypass capacitors as close as possible to the device. layout, grounding, and bypassing the best layout and grounding design always comes from a thorough analysis of the complete system. this includes the signal sources dependence and sensitivi- ty on ground currents, and knowledge of the various currents that could travel through the various potential grounding paths. use pcbs with separate analog and digital ground planes. connect the two ground planes together only at the devices gnd input. isolate the digital supply from the analog with a low-value resistor (10 ) or ferrite bead when the analog and digital supplies come from the same source. ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. a 5ma current flowing through a pcb ground trace impedance of only 0.05 creates an error voltage of approximately 250v. ensure that digital and analog signal lines are kept sepa- rate. do not run digital (especially the sclk and dout) lines parallel to any analog lines or under the devices. lay out the traces in perpendicular directions when a digital line and an analog line cross each other. bypass avdd to the analog ground plane with a 0.1f capacitor in parallel with a 1f to 10f low-esr capac- itor. keep capacitor leads short for best supply-noise rejection. bypass ref+ and ref- with a 0.1f capaci- tor to gnd. place all bypass capacitors as close as possible to the device for optimum decoupling. crystal layout follow these basic layout guidelines when placing a crystal on a pcb with the devices to avoid coupled noise: 1) place the crystal as close as possible to xin and xout. keeping the trace lengths between the crys- tal and inputs as short as possible reduces the probability of noise coupling by reducing the length of the antennae. keep the xin and xout lines close to each other to minimize the loop area of the clock lines. keeping the trace lengths short also decreases the amount of stray capacitance. 2) keep the crystal solder pads and trace width to xin and xout as small as possible. the larger these bond pads and traces are, the more likely it is that noise will couple from adjacent signals. 3) place a guard ring (connect to ground) around the crystal to isolate the crystal from noise coupled from adjacent signals. 4) ensure that no signals on other pcb layers run directly below the crystal or below the traces to xin and xout. the more the crystal is isolated from other signals on the board, the less likely for noise to couple into the crystal. 5) place a local ground plane on the pcb layer imme- diately below the crystal guard ring. this helps to isolate the crystal from noise coupling from signals on other pcb layers. note: keep the ground plane in the vicinity of the crystal only and not on the entire board.
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs 34 ______________________________________________________________________________________ chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 38 tssop u38+3 21-0081 90-0140
max11040k/max11060 24-/16-bit, 4-channel, simultaneous-sampling, cascadable, sigma-delta adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/11 initial release of the max11040k 1 4/11 initial release of the max11060 1 2 11/11 updated absolute maximum ratings 2

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